chp4014 - 98f ref. : dschp40142012 - 12 jan 12 1 / 10 specifications subject to change without notice united monolithic semiconductors s.a.s. bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 5 - 6ghz 6 - bit phase - shifter gaas monolithic microwave ic description the chp4014 - 98f is a 6 - bit digital phase shifter mmic with a 0 - 360 range. it is designed for 5 to 6ghz frequency range applications. the circuit supports a variety of c - band phased array applications including industrial sensors and military radars. the circuit is manufactu red with a power phe mt process, 0.25m gate length. it is available in chip form . main features peak phase error versus state @ 5.5ghz ( wafer measurement) main characteristics tamb. = + 25c symbol parameter min typ max unit fop operating frequency range 5 6 ghz ls insertion loss 6 7 db p1db input power at 1db compression 26 dbm vai (1) voltage control 0 3.3 7 v (1) i=1, 2, 3, 4, 5, and 6 esd protection: electrostatic discharge sensitive device. observe handling precautions! a1 a2 cell 90 cell 5.625 a 3 a 4 v - v+ dc interface cell 11.25 cell 22.5 cell 45 cell 180 a 5 a 6 a1 a2 cell 90 cell 5.625 a 3 a 4 dc interface cell 11.25 cell 22.5 cell 45 cell 180 a 5 a 6 rf_in rf_out
chp4014 - 98f 5 - 6ghz 6 - bit phase - shifter ref. dschp40142012 - 12 jan 12 2 / 10 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 main characteristics tamb. = + 25c symbol parameter min typ max unit fop operating frequency range 5 6 ghz phs phase shifting range 0 360 deg phs step phase shifting step 5.625 deg ppe peak phase error +/ - 4 +/ - 7 deg rmspe _std rms phase error standard deviation 1 2 deg rmspe rms phase error 1 2 deg ls insertion loss 6 7 db lsv insertion loss variation +/ - 0.4 +/ - 0.7 db rl _in input return loss - 10 - 17 db rl _out output return loss - 12 - 20 db p1db input power at 1db c ompression (cw) 26 dbm iip3 input third order intercept 32 dbm ts switching time 20 50 ns v_low control input (a1 - a6) C low level 0 0.4 v v_high control input (a1 - a6) C high level 2.4 3.3 7 v v+ positive supply voltage 5 v v - negative supply voltage - 5 v i+ positive supply current 3.5 10 ma i - negative supply current 3.5 10 ma top operating temperature - 40 +85 deg absolute maximum ratings (1) tamb.= +25c symbol parameter values unit v+ maximum dc positive supply voltage +8 v v - maximum dc positive supply voltage - 8 v ai (2) phase shifter ctrl voltage (v_low, v_high) - 2 , +8 v pin maximum peak input power overdrive +30 dbm top operating temperature range - 40 to +85 c tstg storage temperature range - 55 to +150 c (1) operation of this device above anyone of these parameters may cause permanent damage. (2) i = (1, 2, 3, 4, 5, and 6)
5 - 6ghz 6 - bit phase - shifter chp4014 - 98f ref. : dschp40142012 - 12 jan 12 3 / 10 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 peak phase error (ppe) definition ppe (i) =measured_phase(s21) (i) C measured_phase(s21) (0) C theoretical_phase (i) where (i) is the state (from 0 to 63) rms phase error (rmspe) definition rms_pe= where i is the state number (from 0 to 63). insertion losses variation (lsv) definition lsv (i) =measured_db(s21) (i) C (0) where (i) is the state (from 0 to 63) 64 ) ( 63 0 2 ? ? i i ppe
chp4014 - 98f 5 - 6ghz 6 - bit phase - shifter ref. dschp40142012 - 12 jan 12 4 / 10 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 typical on - wafer results with 0.3nh inductance on input and output [s] parameters tamb.= +25c ; v+=+5v; v - = - 5v s21 versus frequency state 0; 100% wafer s21 versus frequency all phase states, one chip s11 versus frequency all phase states, one chip s22 versus frequency all phase states, one chip
5 - 6ghz 6 - bit phase - shifter chp4014 - 98f ref. : dschp40142012 - 12 jan 12 5 / 10 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 typical on - wafer results phase shifter performances: peak phase error tamb.= +25c; v+=+5v; v - = - 5v peak phase error (deg) versus frequency a ll phase states, one chip peak phase error (deg) versus phase state frequency = [5 C 6ghz], one chip rms phase error peak phase (deg) versus phase state frequency = [5 C 6ghz], one chip
chp4014 - 98f 5 - 6ghz 6 - bit phase - shifter ref. dschp40142012 - 12 jan 12 6 / 10 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 typical on - wafer results phas e shifter performances: insertion loss variation tamb.= +25c; v+=+5v; v - = - 5v insertion loss variation (db ) versus frequency a ll phase states, one chip insertion loss variation (db ) versus phase state frequency = [5 - 6ghz], one chip
5 - 6ghz 6 - bit phase - shifter chp4014 - 98f ref. : dschp40142012 - 12 jan 12 7 / 10 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 mechanical dimensions and pad s allocation unit: m; tolerance: +/ - 35m chip thickness = 100m +/ - 10m rf pads (1, 9) = 122 x 160m2 dc and control pads ( 2, 3, 4, 5, 6, 7, 8, 10, 11, 12) = 100 x 100m2 pin number pad name description 1 in input rf: 3 a1 shifter bit 1 4 a2 shifter bit 2 5 a3 shifter bit 3 6 a4 shifter bit 4 7 a5 shifter r bit 5 8 a6 shifter tor bit 6 9 out output rf 1 0 v - - 5v supply voltage: interface 1 1 v+ +5v supply voltage: interface 2, 12 gnd nc rf_in and rf_out are ac coupled (serie capacitances inside the circuit). 1 2 3 4 5 6 7 8 9 10 11 12
chp4014 - 98f 5 - 6ghz 6 - bit phase - shifter ref. dschp40142012 - 12 jan 12 8 / 10 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 bonding recommendations port connection in (1) out (9 ) inductance (lbonding) = 0.3nh one w ire: diameter 25m, length 0.4m m dc and interface pads inductance (lbonding) = 0.8nh one wire: diameter 25m, length 1 .0 mm recommended assembly diagram in 100pf out - v +v
5 - 6ghz 6 - bit phase - shifter chp4014 - 98f ref. : dschp40142012 - 12 jan 12 9 / 10 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 phase shifter control interface the 6 - bit phase shifter is controlled by 6 control pads (a1 to a6). reference state is 0. state is 0 when 0v is applied, state is 1 when +3.3v is applied. state a1 a2 a3 a4 a5 a6 phase (deg) 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 5,625 2 0 1 0 0 0 0 11,25 3 1 1 0 0 0 0 16,875 4 0 0 1 0 0 0 22,5 5 1 0 1 0 0 0 28,125 6 0 1 1 0 0 0 33,75 7 1 1 1 0 0 0 39,375 8 0 0 0 1 0 0 45 9 1 0 0 1 0 0 50,625 10 0 1 0 1 0 0 56,25 11 1 1 0 1 0 0 61,875 12 0 0 1 1 0 0 67,5 13 1 0 1 1 0 0 73,125 14 0 1 1 1 0 0 78,75 15 1 1 1 1 0 0 84,375 16 0 0 0 0 1 0 90 17 1 0 0 0 1 0 95,625 18 0 1 0 0 1 0 101,25 19 1 1 0 0 1 0 106,875 20 0 0 1 0 1 0 112,5 21 1 0 1 0 1 0 118,125 22 0 1 1 0 1 0 123,75 23 1 1 1 0 1 0 129,375 24 0 0 0 1 1 0 135 25 1 0 0 1 1 0 140,625 26 0 1 0 1 1 0 146,25 27 1 1 0 1 1 0 151,875 28 0 0 1 1 1 0 157,5 29 1 0 1 1 1 0 163,125 30 0 1 1 1 1 0 168,75 31 1 1 1 1 1 0 174,375 32 0 0 0 0 0 1 180 33 1 0 0 0 0 1 185,625 34 0 1 0 0 0 1 191,25 35 1 1 0 0 0 1 196,875 36 0 0 1 0 0 1 202,5 37 1 0 1 0 0 1 208,125 38 0 1 1 0 0 1 213,75 39 1 1 1 0 0 1 219,375 40 0 0 0 1 0 1 225 41 1 0 0 1 0 1 230,625 42 0 1 0 1 0 1 236,25 43 1 1 0 1 0 1 241,875 44 0 0 1 1 0 1 247,5 45 1 0 1 1 0 1 253,125 46 0 1 1 1 0 1 258,75 47 1 1 1 1 0 1 264,375 48 0 0 0 0 1 1 270 49 1 0 0 0 1 1 275,625 50 0 1 0 0 1 1 281,25 51 1 1 0 0 1 1 286,875 52 0 0 1 0 1 1 292,5 53 1 0 1 0 1 1 298,125 54 0 1 1 0 1 1 303,75 55 1 1 1 0 1 1 309,375 56 0 0 0 1 1 1 315 57 1 0 0 1 1 1 320,625 58 0 1 0 1 1 1 326,25 59 1 1 0 1 1 1 331,875 60 0 0 1 1 1 1 337,5 61 1 0 1 1 1 1 343,125 62 0 1 1 1 1 1 348,75 63 1 1 1 1 1 1 354,375
chp4014 - 98f 5 - 6ghz 6 - bit phase - shifter ref. dschp40142012 - 12 jan 12 10 / 10 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 recommended esd management refer to the application note an0020 available at http://www.ums - gaas.com for esd sensitivity and handling recommendations for the ums products. recommended environmental management ums products are compliant with the regulation in particular with the directives rohs n2011/65 and reach n1907/2006. more environmental data are available in the application note an0019 also available at http://www.ums - gaas.com . ordering information chip form : chp4014 - 98f /00 information furnished is believed to be accurate and reliable. however united monolithic semiconductors s.a.s. assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent righ ts of united monolithic semiconductors s.a.s. . specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. united monolithic semiconductors s.a.s. products are not authorised for use as critical components in life support devices or systems without express written approval from united monolithic semiconductors s.a.s.
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